module groupManager (
    input wire clk,
    input wire rst,
    input wire ram_idle_1,                  //RAM�Ŀ���״̬
    input wire ram_idle_2,                  //RAM�Ŀ���״̬
    input wire ram_idle_3,                  //RAM�Ŀ���״̬
    input wire ram_idle_4,                  //RAM�Ŀ���״̬
    input wire ram_idle_5,                  //RAM�Ŀ���״̬
    input wire ram_idle_6,                  //RAM�Ŀ���״̬
    input wire ram_idle_7,                  //RAM�Ŀ���״̬
    input wire ram_idle_8,                  //RAM�Ŀ���״̬
    input wire write_en_1,                  //�˿�1��дʹ��
    input wire [5:0] data_priority_1,       //�˿�1�����ݵ����ȼ�
    input wire [9:0] data_size_1,
    input wire [5:0] data_target_port_1,
    input wire [5:0] data_wait_time_1,      //�˿�1�����ݵĵȴ�ʱ��
    input wire write_en_2,                  //�˿�2��дʹ��
    input wire [5:0] data_priority_2,       //�˿�2�����ݵ����ȼ�
    input wire [9:0] data_size_2,
    input wire [5:0] data_target_port_2,
    input wire [5:0] data_wait_time_2,      //�˿�2�����ݵĵȴ�ʱ��
    input wire write_en_3,                  //�˿�3��дʹ��
    input wire [5:0] data_priority_3,       //�˿�3�����ݵ����ȼ�
    input wire [9:0] data_size_3,
    input wire [5:0] data_target_port_3,
    input wire [5:0] data_wait_time_3,      //�˿�3�����ݵĵȴ�ʱ��
    input wire write_en_4,                  //�˿�4��дʹ��
    input wire [5:0] data_priority_4,       //�˿�4�����ݵ����ȼ�
    input wire [9:0] data_size_4,
    input wire [5:0] data_target_port_4,
    input wire [5:0] data_wait_time_4,      //�˿�4�����ݵĵȴ�ʱ��
    output reg write_en_out,
    output reg [5:0] write_priority_out,
    output reg [9:0] write_size_out,
    output reg [5:0] write_port_out,
    output reg [7:0] pick_ram,
    output reg [3:0] write_arbitration
);
    //仲裁结果
    wire [3:0] port_arbitration;
    wire [7:0] ram_sel;
    //RAM空闲状态整合
    wire [7:0] ram_idle_state;

    assign ram_idle_state = {ram_idle_8, ram_idle_7, ram_idle_6, ram_idle_5, ram_idle_4, ram_idle_3, ram_idle_2, ram_idle_1};

    //对外输出仲裁结果
    always @(posedge clk) begin
        write_arbitration <= port_arbitration;
        pick_ram <= ram_sel;
    end

    always @(posedge clk) begin
        if (write_arbitration == 4'b0001) begin
            write_en_out <= write_en_1;
            write_priority_out <= data_priority_1;
            write_size_out <= data_size_1;
            write_port_out <= data_target_port_1;
        end

        if (write_arbitration == 4'b0010) begin
            write_en_out <= write_en_2;
            write_priority_out <= data_priority_2;
            write_size_out <= data_size_2;
            write_port_out <= data_target_port_2;
        end

        if (write_arbitration == 4'b0100) begin
            write_en_out <= write_en_3;
            write_priority_out <= data_priority_3;
            write_size_out <= data_size_3;
            write_port_out <= data_target_port_3;
        end

        if (write_arbitration == 4'b1000) begin
            write_en_out <= write_en_4;
            write_priority_out <= data_priority_4;
            write_size_out <= data_size_4;
            write_port_out <= data_target_port_4;
        end

        if (write_arbitration == 4'b0000) begin
            write_en_out <= 1'b0;
        end
    end

    //端口写仲裁器
    writeArbiter arb(.write_en_1(write_en_1), .data_priority_1(data_priority_1), .data_wait_time_1(data_wait_time_1), .write_en_2(write_en_2), .data_priority_2(data_priority_2), .data_wait_time_2(data_wait_time_2), .write_en_3(write_en_3), .data_priority_3(data_priority_3), .data_wait_time_3(data_wait_time_3), .write_en_4(write_en_4), .data_priority_4(data_priority_4), .data_wait_time_4(data_wait_time_4), .write_arbitration(port_arbitration));

    //空闲RAM选择器
    writePicker picker(.ram_idle(ram_idle_state), .totle_busy(), .pick_ram(ram_sel));    
endmodule